TF-M vs TF-A — When Do You Reach For Which?
TF-M lives on Cortex-M with SAU and NSC veneers. TF-A lives on Cortex-A with EL3 and BL1/BL2/BL31. Pick by the silicon, not by preference.
TF-M lives on Cortex-M with SAU and NSC veneers. TF-A lives on Cortex-A with EL3 and BL1/BL2/BL31. Pick by the silicon, not by preference.
Why a hardware accelerator and a secure element aren’t substitutes for each other, when one is enough, and when you actually want both.
What SysTick gets right at microsecond resolution, what bites you, and when to reach for a hardware timer instead.
A walk through what TrustZone-M adds to a build: two projects, two memory maps, SAU configuration, the veneer region, and signed images. None of it is gratuitous.
The four usual suspects when code works at -O0 and breaks at -O2, in the order to check them.
Hardware Root of Trust is one of the most-used and least-understood terms in embedded security. What it is, what it isn’t, and how to tell whether a product genuinely has one.
Most secure boot implementations look fine on paper but fail under realistic threat models. Eight common pitfalls — and what fixing them requires.
The six things that happen between reset and main() on a typical Cortex-M, in order, and what goes wrong at each stage.